The present invention relates to a wiring method in layout design of a semiconductor integrated circuit, a semiconductor integrated circuit having a plurality of interconnection lines, and a functional macro.
FIG. 17 schematically illustrates a portion of interconnection lines of a semiconductor integrated circuit placed by a conventional general wiring method. Referring to FIG. 17, the reference numeral 10(0) denotes a lower-order bit interconnection line for the 0-th bit as the least significant bit, 10(1) a lower-order bit interconnection line for the first bit, 10(2) a lower-order bit interconnection line for the second bit, 20(k) a higher-order bit interconnection line for the k-th bit as the most significant bit, 20(kxe2x88x921) a higher-order bit interconnection line for the (kxe2x88x921)th bit, and 20(kxe2x88x922) a higher-order bit interconnection line for the (kxe2x88x922)th bit. These interconnection lines are placed in the ascending order from the least significant 0-th bit or the descending order from the most significant bit. The spacing between the adjacent interconnection lines is set constant. In this placement, the lower-order bits run side by side while the higher-order bits run side by side.
FIG. 19 illustrates a configuration of a functional macro 40 such as a memory to which the k+1 bit interconnection lines 20(k) to 10(0) described above are connected. The functional macro 40 has k+1 terminals 40t(k) to 40t(0) connected to the k+1 bit interconnection lines 20(k) to 10(0) placed in the ascending order from the 0-th bit as the least significant bit (or the descending order from the k-th bit as the most significant bit). Therefore, the terminals 40t(k) to 40t(0) are also placed in the ascending order from the 0-th bit as the least significant bit (or the descending order from the k-th bit as the most significant bit). The k+1 terminals 40t(k) to 40t(0) as a whole transmit or receive information as one unit of data or one address.
FIG. 18 is a diagrammatic illustration of a capacitance between interconnection lines. When two interconnection lines 1 and 2 running in parallel with each other are assumed, a parasitic capacitance is inevitably generated between the two interconnection lines, which is herein called a wiring capacitance 3. When a digital signal on one of two interconnection lines changes from 0 to 1 while a digital signal on the other interconnection line changes in reverse, that is, from 1 to 0, it is called that these signals change to opposite phases. In the parallel interconnection lines 1 and 2 located close to each other, if the signals on these interconnection lines change to opposite phases, they both draw a charge existing in the parasitic capacitance (wiring capacitance 3) formed therebetween. This increases delay in signal propagation.
Semiconductor micro-fabrication technology has advanced at rapid paces. In the level of fine technology before attainment of 0.5 xcexcm, the spacing between interconnection lines was large enough to only generate a small value of parasitic capacitance, and thus there was no occurrence of the problem of increase in signal delay described above. However, at attainment of the level as fine as about 0.35 xcexcm and then about 0.25 xcexcm, this problem began to arise locally in interconnections for high-speed propagation. After attainment of the level of 0.18 xcexcm, this problem has become more significant every time the process is updated. In addition, since it is difficult to correctly grasp what operation the wiring capacitance causes, there has even occurred an unexpected design problem in some cases.
Conventionally, for solving the problem of increase in signal delay, the following techniques, for example, are employed when high-speed operation is required: setting a rule to secure a large spacing between adjacent interconnection lines; providing an additional shield line between adjacent interconnection lines; and twisting (intersecting) interconnection lines.
However, in any of the above techniques of securing a large spacing between interconnection lines, providing a shield line, and twisting interconnection lines, the problem is solved at the expense of increase in the area of the semiconductor integrated circuit. Moreover, when interconnection lines both on which a signal frequently changes (that is, high in signal change frequency) are placed in parallel with each other, the probability that both signals change to opposite phases simultaneously is high. In the conventional wiring method shown in FIG. 17, the lower-order bits tend to be higher in signal change frequency compared with the higher-order bits. Therefore, when interconnection lines for lower-order bits are placed in parallel close to each other as in the configuration shown in FIG. 17, there is significantly high probability that delay in signal propagation may increase due to simultaneous change of signals to opposite phases and this may cause a problem in operation of the semiconductor integrated circuit.
An object of the present invention is providing a wiring method in layout design of a semiconductor integrated circuit having a plurality of interconnection lines, capable of effectively suppressing delay in signal propagation due to signal interference between the plurality of parallel interconnection lines while minimizing increase in area, and a semiconductor integrated circuit and a functional macro capable of effectively suppressing interference between signals described above.
To attain the above object, according to the present invention, attention is paid to the fact that when a plurality of interconnection lines are provided, signals propagating through the interconnection lines are different in signal change frequency, in particular, in multi-bit interconnection lines, signal lines for higher-order bits are considerably low in signal change frequency compared with signal lines for lower-order bits. In view of this fact, these interconnection lines, as well as a plurality of terminals of a functional macro connected to these interconnection lines, may be suitably placed based on the change frequency of the signals propagating through these interconnection lines. By this placement, interference between the signals can be effectively suppressed.
The wiring method in layout design of a semiconductor integrated circuit of the present invention is a method for placing interconnection lines for a plurality of bits in parallel two-dimensionally or three-dimensionally in layout design of a semiconductor integrated circuit, wherein the interconnection lines for a plurality of bits are placed in an ascending or descending order of the bits, interconnection lines for bits of ordinal numbers equal to or more than a predetermined ordinal number are placed adjacent to each other at a predetermined spacing, and interconnection lines for bits of ordinal numbers less than the predetermined ordinal number are placed adjacent to each other at a spacing exceeding the predetermined spacing.
Alternatively, the wiring method in layout design of a semiconductor integrated circuit of the present invention is a method for placing interconnection lines in parallel two-dimensionally or three-dimensionally in layout design of a semiconductor integrated circuit, wherein a signal change frequency at which a signal propagating through an interconnection line changes per unit time is determined for each of the plurality of interconnection lines by estimation or simulation, and the plurality of interconnection lines are placed based on the signal change frequency so that interconnection lines having a high signal change frequency and interconnection lines having a low signal change frequency are adjacent to each other.
In the method described above, in the case of transmitting a signal of a plurality of bits via the plurality of interconnection lines, the plurality of interconnection lines may be placed based on the signal change frequency, irrespective of an ascending or descending order of the bits.
In the method described above, the plurality of interconnection lines may be placed so that interconnection lines having a high signal change frequency are sandwiched by interconnection lines having a low signal change frequency.
Alternatively, the wiring method in layout design of a semiconductor integrated circuit of the present invention is a method for placing interconnection lines for a plurality of bits in parallel two-dimensionally or three-dimensionally in layout design of a semiconductor integrated circuit, wherein in placement of the interconnection lines for a plurality of bits, one interconnection line for a bit of an ordinal number equal to or more than a predetermined ordinal number and an interconnection line for a bit of an ordinal number less than the predetermined ordinal number are placed adjacent to each other, and another interconnection line for a bit of an ordinal number equal to or more than the predetermined ordinal number and another interconnection line for a bit of an ordinal number less than the predetermined ordinal number are placed adjacent to each other, and this placement is repeated.
In the method described above, preferably, interconnection lines for bits are placed in a descending order from the most significant bit until a bit of the predetermined ordinal number in parallel two-dimensionally at a spacing double a predetermined spacing, and interconnection lines for bits are placed in an ascending order from the least significant bit in parallel two-dimensionally between the already-placed interconnection lines.
In the wiring method described above, the method may include the steps of: (1) placing an interconnection line for the least significant bit at a predetermined position; (2) placing interconnection lines for the two highest-order bits on the right and left sides of the interconnection line for the least significant bit; (3) placing interconnection lines for the remaining two lowest-order bits on the right and left sides of the interconnection lines for the two highest-order bits placed in the step (2); (4) placing interconnection lines for the remaining two highest-order bits on the right and left sides of the interconnection lines for the two lowest-order bits placed in the step (3); and (5) repeating the steps (3) and (4) until the interconnection lines for all the bits are placed.
Alternatively, the wiring method in layout design of a semiconductor integrated circuit of the present invention is a method for placing interconnection lines for a plurality of bits in parallel three-dimensionally in n wiring layers (n greater than 2) in layout design of a semiconductor integrated circuit. The method includes the steps of: (1) placing an interconnection line for the least significant bit in a predetermined wiring layer; (2) placing interconnection lines for a plurality of highest-order bits in the same wiring layer as the interconnection line for the least significant bit and a different wiring layer so as to surround the interconnection line for the least significant bit placed in the step (1); (3) placing interconnection lines for a plurality of remaining lowest-order bits in the same wiring layers as the interconnection lines for a plurality of highest-order bits and a different wiring layer so as to surround the interconnection lines for a plurality of highest-order bits placed in the step (2); and (4) repeating the steps (2) and (3) until the interconnection lines for all the bits are placed.
In the method described above, preferably, the n wiring layers are two wiring layers, the interconnection line for the least significant bit is placed at a predetermined position of the lower wiring layer in the step (1), interconnection lines for the three highest-order bits are placed in the lower and upper wiring layers so as to be positioned on the right, left and upper sides of the interconnection line for the least significant bit in the step (2); interconnection lines for the remaining four lowest-order bits are placed in the lower and upper wiring layers so as to be positioned on the right and left sides of the interconnection lines for the three highest-order bits in the step (3), and the steps (2) and (3) are repeated until the interconnection lines for all the bits are placed in the step (4).
In the method described above, preferably, the n wiring layers are two wiring layers, the interconnection line for the least significant bit is placed at a predetermined position of the upper wiring layer in the step (1), interconnection lines for the three highest-order bits are placed in the upper and lower wiring layers so as to be positioned on the right, left and lower sides of the interconnection line for the least significant bit in the step (2); interconnection lines for the remaining four lowest-order bits are placed in the upper and lower wiring layers so as to be positioned on the right and left sides of the interconnection lines for the three highest-order bits in the step (3), and the steps (2) and (3) are repeated until the interconnection lines for all the bits are placed in the step (4).
In the method described above, preferably, the n wiring layers are three wiring layers, the interconnection line for the least significant bit is placed at a predetermined position of the center wiring layer in the step (1), interconnection lines for the four highest-order bits are placed in the center, lower and upper wiring layers so as to be positioned on the right, left, upper and lower sides of the interconnection line for the least significant bit in the step (2); interconnection lines for the remaining six lowest-order bits are placed in the center, lower and upper wiring layers so as to be positioned on the right and left sides of the interconnection lines for the four highest-order bits in the step (3), interconnection lines for the remaining six highest-order bits are placed in the center, lower and upper wiring layers so as to be positioned on the right and left sides of the interconnection lines for the six lowest-order bits in the step (4), and the steps (3) and (4) are repeated until the interconnection lines for all the bits are placed.
The semiconductor integrated circuit of the present invention is a semiconductor integrated circuit having interconnection lines for a plurality of bits placed in an ascending or descending order of the bits in parallel two-dimensionally or three-dimensionally, wherein the spacing between interconnection lines for bits of ordinal numbers less than a predetermined ordinal number is larger than the spacing between interconnection lines for bits of ordinal numbers equal to or more than the predetermined ordinal number.
Alternatively, the semiconductor integrated circuit of the present invention is a semiconductor integrated circuit having a plurality of interconnection lines placed in parallel two-dimensionally or three-dimensionally, wherein the plurality of interconnection lines are not arranged in an ascending or descending order of a signal change frequency at which a signal propagating through an interconnection line changes.
In the semiconductor integrated circuit described above, preferably, the plurality of interconnection lines are interconnection lines for a plurality of bits, and the interconnection lines for a plurality of bits are placed in an order irrespective of an ascending or descending order of the bits.
In the semiconductor integrated circuit described above, an interconnection line having a high signal change frequency is preferably sandwiched by two interconnection lines having a low signal change frequency.
In the semiconductor integrated circuit described above, the width of the plurality of interconnection lines is preferably 0.18 xcexcm or less.
In the semiconductor integrated circuit described above, the plurality of interconnection lines may be a plurality of address bus lines.
In the semiconductor integrated circuit described above, signals propagating through the plurality of interconnection lines may be digital signals of an image or voice.
Alternatively, the semiconductor integrated circuit of the present invention is a semiconductor integrated circuit including: a plurality of interconnection lines; a processing circuit for performing predetermined processing and outputting signals of results of the predetermined processing to the plurality of interconnection lines; and switch means disposed between the plurality of interconnection lines and the processing circuit for changing the order of arrangement of the signals output from the processing circuit so that the signals are not arranged in an ascending or descending order of a signal change frequency and transmitting the signals in the changed order to the plurality of interconnection lines.
The semiconductor integrated circuit described above may further include: a receiver circuit for receiving the signals transmitted through the plurality of interconnection lines; and second switch means disposed between the plurality of interconnection lines and the receiver circuit for changing the order of arrangement of the signals transmitted through the plurality of interconnection lines to the ascending or descending order of the signal change frequency and transmitting the signals in the changed order to the receiver circuit.
The functional macro of the present invention is a functional macro having a plurality of terminals to which interconnection lines for a plurality of bits are connected, wherein the plurality of terminals are placed in an ascending or descending order of the bits, the spacing between terminals for higher-order bits among the plurality of terminals is set at a predetermined spacing, and the spacing between terminals for lower-order bits among the plurality of terminals is set at a spacing larger than the predetermined spacing.
Alternatively, the functional macro of the present invention is a functional macro having a plurality of terminals to which interconnection lines for a plurality of bits are connected, wherein the order of arrangement of the plurality of terminals does not depend on an ascending or descending order of the bits, but is set based on a change frequency of signals input into or output from the terminals.
In the functional macro described above, preferably, the plurality of terminals are placed so that a terminal having a high signal change frequency is sandwiched by terminals having a low signal change frequency.
In the functional macro described above, preferably, terminals for higher-order bits of ordinal numbers equal to or more than a predetermined ordinal number are placed in a descending order from the most significant bit at a spacing double a predetermined spacing, and terminals for lower-order bits of ordinal numbers less than the predetermined ordinal number are placed in an ascending order from the least significant bit between the terminals for the higher-order bits starting from the side of the terminal for the most significant bit.
In the functional macro described above, terminals for given two bits continuous from the least significant position may be placed on the inner or outer sides of terminals for given two bits continuous from the most significant position.
In the functional macro described above, preferably, two terminals for the two highest-order bits are placed on both ends, and two terminals for the two lowest-order bits are placed on the inner sides of the two terminals for the two highest-order bits.
In the functional macro described above, a terminal for the least significant bit is preferably placed on the center of the plurality of terminals placed.
Alternatively, the semiconductor integrated circuit of the present invention is a semiconductor integrated circuit including: a functional macro having a plurality of terminals arranged in an ascending or descending order of bits, other terminals identical in number to the plurality of terminals placed in correspondence with the plurality of terminals, the other terminals being arranged in an order based on a signal change frequency; and a terminal sorting block for connecting the plurality of terminals of the functional macro to the other terminals.
In the semiconductor integrated circuit described above, the functional macro, the other terminals and the terminal sorting block may be formed integrally.
In the functional macro described above, the functional macro may be a memory, an operator or a CPU.
Alternatively, the wiring method of the present invention is a wiring method in layout design of a semiconductor integrated circuit, wherein a plurality of interconnection lines are connected to the plurality of terminals of the functional macro described above, and an interconnection line on which a signal changes frequently among the plurality of interconnection lines is sandwiched by two interconnection lines on which a signal changes less frequently.
Alternatively, the semiconductor integrated circuit of the present invention is a semiconductor integrated circuit including, two or more functional macros described above; and a plurality of interconnection lines for connecting the plurality of terminals of the functional macros to each other, wherein an interconnection line on which a signal changes frequently among the plurality of interconnection lines is sandwiched by two interconnection lines on which a signal changes less frequently.
In the semiconductor integrated circuit described above, preferably, three or more functional macros are provided, and the plurality of interconnection lines are address bus lines for a plurality of bits.
In the semiconductor integrated circuit described above, preferably, two functional macros are provided, one of the two functional macros being an A/D converter, and the plurality of interconnection lines are data signal interconnection lines for transmitting a digital signal output from the A/D converter by converting an analog value to a digital value.
Thus, according to the present invention, in placement of interconnection lines for a plurality of bits in the ascending or descending order of the bits, the spacing between interconnection lines for lower-order bits of ordinal numbers less than a predetermined ordinal number having a high signal change frequency is set large so that the wiring capacitance between the interconnection lines is small. This effectively suppresses or eliminates a problem in operation of a semiconductor integrated circuit that may occur due to increase in delay caused by change of signals to opposite phases between the interconnection lines. Moreover, the spacing between interconnection lines for higher-order bits of ordinal numbers equal to or more than the predetermined ordinal number having a low signal change frequency is set smaller than the above largely-set spacing. This effectively suppresses increase in the area of the semiconductor integrated circuit compared with the case of setting the large spacing for all the interconnection lines.
According to the present invention, in placement of a plurality of interconnection lines, interconnection lines having a high signal change frequency and interconnection lines having a low signal change frequency are placed to be adjacent to each other. Therefore, the interconnection lines having a low signal change frequency serve like shield lines for the interconnection lines having a high signal change frequency. This also minimizes the probability that signals on two interconnection lines may change to opposite phases. As a result, it is possible to effectively suppress or eliminate a problem in operation of a semiconductor integrated circuit that may occur due to change of signals to opposite phases between interconnection lines having a high signal change frequency. Since only the order of arrangement of signals propagating through the plurality of interconnection lines is changed, undesired increase in the area of the semiconductor integrated circuit is prevented.
According to the present invention, once an auto placing and routing tool grasps the order of arrangement of terminals of a functional macro, automatic layout of interconnection lines for lower-order bits and interconnection lines for higher-order bits in the order of arrangement of the terminals is possible by normal automatic routing using the auto placing and routing tool. Therefore, the interconnection lines having a low signal change frequency serve like shield lines for the interconnection lines having a high signal change frequency, and increase in delay in signal propagation due to signal interference can be effectively suppressed without undesired increase in the area of the entire semiconductor integrated circuit.